A dedicated integrated circuit that walks a persistent typed event‑graph memory through hardware‑bounded arithmetic on decay‑adjusted link weights — within a milliwatt‑scale power budget built for wearables, vehicles, the home, and licensed SoC blocks.
Personal AI assistants need a persistent memory they can recall in milliseconds. But the chips we have were built for other workloads — and they pay for the mismatch in power and latency.
Evaluate every typed link in software — instruction fetch, memory access, and ALU cycles stacked per edge. The control overhead dwarfs the value of the weight produced.
Tuned for dense, contiguous tensor math. Graph traversal is sparse, irregular, and data-dependent — so these engines sit idle while their datapaths starve.
Designed for graphs orders of magnitude larger, drawing tens to hundreds of watts. Wholly incompatible with a device you wear on your face all day.
None implement dedicated units for decay-adjusted link weights, decay-profile evaluation, hardware ranking, or traversal-aware caching. It all falls back to software.
Every block is a fixed-function structure measured in pipeline cycles, coordinated by an on-chip state machine that runs while the host application processor sleeps. Tap a block in the floorplan to inspect it.
Five link attributes and an elapsed-time input are folded together through a decay function in a fixed-function datapath. What takes a CPU dozens of cycles, the GTX-1 resolves in one — or a handful.
Each typed link names a decay-profile type; the decay-evaluation block routes it to the matching hardware function, parameterized by per-link coefficients.
The persistent event-graph memory holds two record types. Highlighted fields feed directly into the decay-adjusted weight computation.
The GTX-1 is framed as a discrete component — not an inseparable part of a product — so it can drop into wearables, cabins, homes, and third-party silicon alike.
Smart-glasses, earbuds, smartwatches and other body-worn devices.
In-cabin AI, driver assistance, autonomous decision-support and fleet.
Ambient assistance and occupant interaction in the connected home.
Worker-context recall and operational decision-support on the floor.
Clinician-facing patient recall under regulatory-compliance constraints.
Paired peer devices, each running an instance, sharing memory updates.
Licensed to semiconductor vendors as a block of a mobile-processor SoC.
Integrity-signed records, consent gating, raw sensor data never leaves.
The functional relationships hold across every manufacturing path — the engine speaks one request–result protocol regardless of how it's built.
A single semiconductor die on a dedicated process node, packaged with its own contacts to external systems.
Integrated as a chiplet through industry-standard interconnect, alongside other dies in one package.
A block within a general-purpose SoC sitting next to CPU cores, NPUs, modems, and crypto co-processors.
Wireless transceivers — external to the IC — exchange federated update signals that carry only changes to link attributes, omitting any raw captured data.
The federation hub aggregates updates, distributes relevant changes per device-pairing and consent gating, and propagates right-to-erasure through tombstone and correction records.
External AI agents reach memory elements only after authentication, cryptographic attestation of context, and consent-based authorization.
Event-graph memories nest across individuals, groups, organizations, and consortia — each level with its own scope-governance policies.
GTX‑1 does not store the event‑graph; it traverses one. Its dedicated memory interface is designed to pair with Priver Engram, a graph‑native compute‑in‑memory array that maintains the graph in place. Together they form the memory engine inside Priver Core: Engram stores and ages the links; GTX‑1 fetches, computes decay‑adjusted weights, and ranks candidates.
Stores the typed event‑graph; ages, grows, and reinforces links in place; returns decay‑adjusted weights and candidate nodes.
Walks the graph over the dedicated memory interface, computes link‑weight arithmetic in hardware, and selects what the inference layer sees next.
A graph-traversal accelerator integrated circuit comprising sparse-graph fetch, link-weight arithmetic, decay-evaluation and candidate-node ranking circuitry, a traversal-control state machine, a local cache, and a request-result interface — all within an integrated-circuit boundary, coupled to a persistent typed event-graph memory through a dedicated memory interface. The link-weight arithmetic computes decay-adjusted weights as a hardware-bounded operation combining link weight, confidence, recurrence count, temporal activation, and elapsed time through a decay function. A power-management interface holds the part at milliwatt-scale through clock-gating, power-gating, dynamic voltage and frequency scaling, and duty-cycle management. Implementable as a standalone ASIC, a chiplet, or an SoC block.